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PHK18NQ03LT
N-channel TrenchMOS logic level FET
Rev. 01 -- 18 December 2006 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology.
1.2 Features
I Optimized for use in DC-to-DC converters I Logic level compatible I Very low switching and conduction losses
1.3 Applications
I DC-to-DC converters I Voltage regulators I Switched-mode power supplies I Notebook computers
1.4 Quick reference data
I VDS 30 V I RDSon 8.9 m I ID 20.3 A I QGD = 2.5 nC (typ)
2. Pinning information
Table 1. Pin 1, 2, 3 4 5, 6, 7, 8 Pinning Description source (S) gate (G) drain (D)
8 5
D
Simplified outline
Symbol
G
mbb076
1
4
S
SOT96-1 (SO8)
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2. Ordering information Package Name PHK18NQ03LT SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number
4. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage drain-gate voltage (DC) gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tsp = 25 C Tsp = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 31.5 A; tp = 0.07 ms; VDS 25 V; RGS = 50 ; VGS = 10 V; starting at Tj = 25 C Tsp = 25 C; VGS = 10 V; see Figure 2 and 3 Tsp = 100 C; VGS = 10 V; see Figure 2 Tsp = 25 C; pulsed; tp 10 s; see Figure 3 Tsp = 25 C; see Figure 1 Conditions 25 C Tj 150 C 25 C Tj 150 C; RGS = 20 k Min -55 -55 Max 30 30 20 20.3 12.1 80 6.25 +150 +150 5.2 20.8 50 Unit V V V A A A W C C A A mJ
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
2 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
120 Pder (%) 80
03aa17
120 Ider (%) 80
03aa25
40
40
0 0 50 100 150 Tsp (C) 200
0 0 50 100 150 Tsp (C) 200
P tot P der = ----------------------- x 100 % P tot ( 25C ) Fig 1. Normalized total power dissipation as a function of solder point temperature
103 ID (A) 102
ID I der = ------------------- x 100 % I D ( 25C ) Fig 2. Normalized continuous drain current as a function of solder point temperature
003aaa680
Limit RDSon = VDS / ID
tp = 10 s 100 s 10 1 ms DC 10 ms 1 100 ms
10-1 10-1
1
10
VDS (V)
102
Tsp = 25 C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
3 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4. Rth(j-sp) Thermal characteristics Conditions see Figure 4 Min Typ Max 20 Unit K/W thermal resistance from junction to solder point Symbol Parameter
102 Zth(j-sp) (K/W) 10 = 0.5 0.2 0.1 1 0.05 0.02 single pulse 10
-1
003aaa681
P
=
tp T
tp T
t
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
4 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5. Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 C Tj = 150 C Tj = -55 C IDSS drain leakage current VDS = 30 V; VGS = 0 V Tj = 25 C Tj = 150 C IGSS RG RDSon gate leakage current gate resistance drain-source on-state resistance VGS = 16 V; VDS = 0 V f = 1 MHz; VGSS(AC) = 150 mV VGS = 10 V; ID = 25 A; see Figure 6 and 8 Tj = 25 C Tj = 150 C VGS = 4.5 V; ID = 25 A; see Figure 6 and 8 Dynamic characteristics QG(tot) QGS QGS1 QGS2 QGD VGS(pl) Ciss Coss Crss Ciss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge pre-VGS(th) gate-source charge post-VGS(th) gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance input capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 20 A; VGS = 0 V; see Figure 13 IS = 15 A; dIS/dt = -100 A/s; VGS = 0 V VGS = 0 V; VDS = 0 V; f = 1 MHz VDS = 12 V; RL = 0.8 ; VGS = 4.5 V; RG = 5.6 VGS = 0 V; VDS = 12 V; f = 1 MHz; see Figure 14 ID = 15 A; VDS = 12 V; VGS = 4.5 V; see Figure 11 and 12 10.6 4.85 2.4 2.45 2.5 3 1380 290 135 1590 19 22 19 11 0.95 34 14 1.2 nC nC nC nC nC V pF pF pF pF ns ns ns ns V ns nC 7.1 12.1 10.1 8.9 15.1 12.5 m m m 1.6 1 100 100 A A nA 1.3 0.8 1.7 2.15 2.6 V V V 30 27 V V Conditions Min Typ Max Unit
Source-drain diode
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
5 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
20 ID (A) 15
003aaa682
10 4.5 3.4
3.2
50 RDSon (m) VGS (V) = 2.8
003aaa684
3
3
40
30 10 2.8 20 3.4 5 2.6 VGS (V) = 2.4 0 0 0.2 0.4 0.6 VDS (V) 0.8 0 0 5 10 15 ID (A) 20 10 4.5 10 3.2
Tj = 25 C
Tj = 25 C
Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values
40 ID (A) 30
003aaa683
Fig 6. Drain-source on-state resistance as a function of drain current; typical values
2 a 1.6
003aab467
1.2 20 0.8 10
Tj = 150 C
25 C
0.4
0 0 1 2 3 VGS (V) 4
0 -60
0
60
120
Tj (C)
180
Tj = 25 C and 150 C; VDS > ID x RDSon
R DSon a = ----------------------------R DSon ( 25C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature
Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
6 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
3 VGS(th) (V) 2.5 max 2 typ 1.5 min
003aab272
10-3 ID (A) 10-4
003aab271
min
typ
max
1
10-5
0.5
0 -60
10-6 0 60 120 Tj (C) 180 0 0.5 1 1.5 2 VGS (V) 2.5
ID = 1 mA; VDS = VGS
Tj = 25 C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of junction temperature
10 VGS (V) 8 ID = 15 A Tj = 25 C
003aaa685
Fig 10. Sub-threshold drain current as a function of gate-source voltage
VDS ID
6 12 V
VDS = 19 V
VGS(pl)
4
VGS(th)
2
VGS QGS1 QGS2 QGD QG(tot)
003aaa508
0 0 5 10 15 20 25 QG (nC)
QGS
ID = 15 A; VDS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Gate charge waveform definitions
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
7 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
40 IS (A) 30
003aaa686
104
003aaa687
C (pF)
Ciss 20 103
10
150 C
Tj = 25 C
Coss Crss 1 10 VDS (V) 102
0 0 0.4 0.8 VSD (V) 1.2
102 10-1
Tj = 25 C and 150 C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain voltage; typical values
Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
003aaa688
104
C (pF) Ciss Crss 10
3
102 10-1
1
VGS (V)
10
VGS = 0 V; f = 1 MHz
Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
8 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
7. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 16. Package outline SOT96-1 (SO8)
PHK18NQ03LT_1 (c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
9 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 6. Revision history Release date 20061218 Data sheet status Product data sheet Change notice Supersedes Document ID PHK18NQ03LT_1
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
10 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
PHK18NQ03LT_1
(c) NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 -- 18 December 2006
11 of 12
NXP Semiconductors
PHK18NQ03LT
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 December 2006 Document identifier: PHK18NQ03LT_1

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